Nonvolatile Memory And Writing Method Thereof, And Semiconductor Device

ABSTRACT

A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/756,342, filed Apr. 8, 2010, now allowed, which is a divisional ofU.S. application Ser. No. 11/612,069, filed Dec. 18, 2006, now U.S. Pat.No. 7,719,872, which claims the benefit of a foreign priorityapplication filed in Japan as Serial No. 2005-377260 on Dec. 28, 2005,all of which are incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory. In particular,the present invention relates to a nonvolatile memory having a pluralityof memory cells that can be written once (also referred to as anonvolatile semiconductor memory).

2. Description of the Related Art

As a semiconductor memory, there are a DRAM (Dynamic Random AccessMemory), a SRAM (Static Random Access Memory), a flash memory, an EEPROM(Electrically Erasable Programmable Read Only Memory), and the like. Asthese memories have large capacities, there is high probability that adefective bit exists even in an advanced manufacturing process. As for aconventional large capacity memory, a redundant circuit is provided anda defective bit is modified after manufacturing a chip; therefore, ayield may be improved and the cost may be reduced. Specifically, amemory is inspected before the shipment. When there is a defective bit,such setting that an fuse within a redundant circuit is disconnected isconfigured for a memory having the defective bit, and the memory isshipped after restoring the defective bit (for example, see Reference 1:Keeth Baker, “DRAM: Circuit Design A TUTORIAL”, IEEE PRESS, 2001,P.108-109).

SUMMARY OF THE INVENTION

As one kind of semiconductor memory, there is a nonvolatile memoryhaving a plurality of memory cells that can be written only once, whichis referred to as a write-once memory, a one time programmable memory,or the like. The write-once memory can be written only once to eachmemory cell; therefore, a defective bit cannot be detected by an actualinspection of writing. In other words, there is a problem that anon-defective memory and a defective memory cannot be distinguisheduntil the memories are used. Accordingly, as described above, themeasures, in which a redundant circuit is provided and the defective bitis modified before shipping, cannot be taken; thus, it is difficult toprovide a memory with few defects.

In view of the above problem, it is an object of the present inventionto provide a write-once memory where the probability of a defect isreduced considerably.

As described above, since the defective bit of the write-once memorycannot be inspected before shipping, it is required to reduce theprobability of the defective bit considerably. Thus, the inventor hasconsidered including a series of operations of detecting the defectivebit and modifying the defective bit as the writing operation of thewrite-once memory, in addition to the operation of writing data, so thatthe probability that the defective bit is generated is reduced.

Hereinafter, a specific structure of the present invention will bedescribed.

According to one mode of a nonvolatile memory of the present invention,the nonvolatile memory includes a memory cell array having a pluralityof memory cells including a redundant memory cell; a first circuit whichallocates an address to the redundant memory cell; a second circuitwhich outputs a determination signal that expresses whether writing isperformed normally or not; and a third circuit, to which thedetermination signal is input, which controls the first circuit and thesecond circuit.

According to another mode of a nonvolatile memory of the presentinvention, the nonvolatile memory includes a data register; a firstwriting circuit; a reading circuit; a bit-line driver circuit; a wordline driver circuit; a memory cell array having a plurality of memorycells including a redundant memory cell; a verifying circuit; a secondwriting circuit which allocates an address to the redundant memory cell;and a timing control circuit. The verifying circuit outputs adetermination signal by comparing data stored in the data register anddata stored in the memory cell. The timing control circuit, to which thedetermination signal is input, outputs at least a first control signal,a second control signal, a third control signal, and a fourth controlsignal. The first control signal is input to the verifying circuit. Thesecond control signal is input to the second writing circuit. The thirdcontrol signal is input to the first writing circuit. The fourth controlsignal is input to the reading circuit.

According to the nonvolatile memory of the present invention, each ofthe plurality of memory cells may have a memory element and the memoryelement may have an organic layer.

According to another mode of the present invention, a semiconductordevice having a communication function, where the nonvolatile memory isincorporated, is provided.

According to another mode of the present invention, a semiconductordevice having a communication function formed over a flexible substrate,where the nonvolatile memory is incorporated, is provided.

According to another mode of the present invention, the following wherethe semiconductor device is mounted is provided: paper money, a coin,securities, a certificate, a bearer bond, a packaging container, a book,recording media, a vehicle, food, clothing, a health product, acommodity, a chemical, or an electronic device.

According to one mode of a method for writing a nonvolatile memory, themethod includes the steps of a first step of writing first data to afirst address; a second step of comparing second data stored in thefirst address after the first step with the first data; a third step ofallocating the first address to a redundant memory cell in a case wherethe result of the second step discords; and a fourth step of writing thefirst data to the redundant memory cell after the third step.

According to the structure and the writing method of the presentinvention, a write-once memory with few defects is provided.

In addition, a semiconductor device, which is formed over a flexiblesubstrate, has a communication function, where a nonvolatile memory ofthe present invention is incorporated. Without data rewritten, thesemiconductor device can realize a high level of security with fewdefects.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram of a semiconductor memory of the presentinvention;

FIG. 2 is a flow chart expressing the writing operation of asemiconductor memory of the present invention;

FIG. 3 is a diagram explaining the configuration of a word line drivercircuit included in a semiconductor memory of the present invention;

FIGS. 4A and 4B are timing charts each expressing the writing operationof a semiconductor memory of the present invention;

FIG. 5 is a diagram explaining the configuration of a word line drivercircuit included in a semiconductor memory of the present invention;

FIG. 6 is a block diagram of a semiconductor memory of the presentinvention;

FIG. 7 is a diagram explaining the configuration of a word line drivercircuit included in a semiconductor memory of the present invention;

FIG. 8 is a diagram explaining the configuration of a verifying circuitincluded in a semiconductor memory of the present invention;

FIG. 9 is a block diagram of a semiconductor device where asemiconductor memory of the present invention is incorporated;

FIGS. 10A and 10B are each a block diagram of a semiconductor memory;

FIGS. 11A and 11B are views each explaining a method for manufacturing asemiconductor device of the present invention;

FIGS. 12A and 12B are views each explaining a method for manufacturing asemiconductor device of the present invention;

FIGS. 13A and 13B are each a top view and a cross-sectional view of asemiconductor device of the present invention; and

FIGS. 14A to 14H are views each showing an application mode of asemiconductor device of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment modes of the present invention will be explained hereinafterwith reference to the accompanying drawings. However, it is to be easilyunderstood that various changes and modifications will be apparent tothose skilled in the art. Therefore, unless such changes andmodifications depart from the purpose and the scope of the presentinvention, they should be construed as being included therein. Note thatthe same portions or portions having the same function in all figuresfor explaining embodiment modes are denoted by the same referencenumerals and detailed explanations thereof will be omitted.

Embodiment Mode 1

This embodiment mode will explain the structure and operation of awrite-once memory of the present invention.

First, an example of the structure and operation of a write-once memory,where the operation of standard writing is performed, will be explained.Here, a memory element, the initial state of which is in highresistance, can be written when a voltage of 6V is applied. The memoryelement is to have a characteristic to be in a low-resistant state afterwritten. As the memory element, a structure where an inorganic film oran organic film is provided between electrodes can be employed.

FIG. 10A is an example of a block diagram of a write-once memory, wherea memory 1001 has a reading/writing circuit 1002, a bit line drivercircuit 1003, a word line driver circuit 1007, and a memory cell array1010. The bit line driver circuit 1003 has a column decoder 1004, alevel shifter 1005, and a selector 1006. The word line driver circuit1007 has a row decoder 1008 and a level shifter 1009. FIG. 10B is acircuit diagram of a memory cell included in the memory cell array 1010.A memory cell 1011 includes a select transistor 1012 and a memoryelement 1013. One of a source electrode and a drain electrode of theselect transistor is connected to a bit line, the other electrode isconnected to one electrode of the memory element 1013, and a gateelectrode of the select transistor is connected to a word line,respectively. In addition, the other electrode of the memory element1013 is connected to a common electrode (potential Vc).

A write enable signal (WE), a read enable signal (RE), a clock signal(CLK), an address signal (ADR), and an input data signal (DATAIN) areinput to the write-once memory shown in FIGS. 10A and 10B, and an outputdata signal (DATAOUT) is output. When the write enable signal (WE) isasserted, a memory cell specified by the address signal is selected;therefore, the input data is written to the selected memory cell. Inaddition, when the read enable signal (RE) is asserted, a memory cellspecified by the address signal is selected; therefore, the data storedin the selected memory cell is read as the output data signal (DATAOUT).Since the memory of the present invention is the write-once memory, itshould not be possible to assert the write enable signal and to inputthe input data signal before shipping, in order to inspect and modifythe defective bit. Accordingly, in the write-once memory of the presentinvention, the user of the memory may assert the write enable signal.Further, the input data signal may not be the data signal for inspectingthe defective bit.

The address signal is input to the column decoder 1004, and a signalline of a specified column is selected. The level shifter 1005 changesthe voltage level of the signal line, if necessary. The selector 1006drives the switch of the column selected by the column decoder 1004, andconnects the bit line and reading/writing circuit 1002. The addresssignal is input to the row decoder 1008, and a signal line of aspecified row is selected. The level shifter 1009 changes the voltage ofthe signal line, if necessary. Consequently, predetermined potential isinput to the selected word line.

For example, at the time of writing, the selected memory cell has thebit line and the word line each given with a voltage of 6V, and thecommon electrode given with a voltage of 0V. Consequently, the selecttransistor 1012 is turned on, and a voltage of approximately 6V isapplied to the memory element 1013; therefore, element characteristics(resistance or the like) of the memory element 1013 is changed. Inaddition, at the time of reading, the selected memory cell has the wordline and the common electrode given with voltages of 3V and 0V,respectively; therefore, the select transistor 1012 is turned on.Accordingly, the selected bit line is connected to the reading circuit.Consequently, the stored data is read in accordance with elementcharacteristics (a high-resistant state, a low-resistant state, or thelike) of the memory element 1013.

As described through the above, a write-once memory, where the operationof standard writing is performed, is formed, and the operation ofwriting or reading is performed.

Next, an example of the structure and operation of the write-once memoryof the present invention will be explained. FIG. 1 is an example of ablock diagram of the write-once memory of the present invention, where amemory 101 has a reading/writing/verifying circuit 102, a bit linedriver circuit 107, a word line driver circuit 108, a memory cell array109, a second writing circuit 110, and a timing control circuit 111. Thereading/writing/verifying circuit 102 has a reading/writing circuit 104,a verifying circuit 105, and a data register 106. A writing circuit inthe reading/writing circuit 104 is also referred to as a first writingcircuit.

As compared with a write-once memory of general, the write-once memoryof the present invention includes, as its structure, the memory cellarray 109 having a redundant memory cell and a driver circuit of thememory cell array 109 corresponding to the redundant memory cell. Inaddition, the write-once memory of the present invention also includesthe verifying circuit 105 that confirms the result of the writing; thesecond writing circuit 110 that allocates the address to the redundantmemory cell; and the timing control circuit 111 that controls thereading/writing/verifying circuit 102, the second writing circuit 110,the bit line driver circuit 107, and the word line driver circuit 108.Moreover, a determination signal output from the verifying circuit 105is input to the timing control circuit 111.

A write enable signal (WE), a read enable signal (RE), a clock signal(CLK), an address signal (ADR), and an input data signal (DATAIN) areinput to the memory 101, and an output data signal (DATAOUT) is output.The reading operation is performed by asserting the read enable signal(RE). When the read enable signal (RE) is asserted, a memory cellspecified by the address signal is selected; therefore, the data storedin the selected memory cell is read as the output data signal (DATAOUT).

FIG. 2 shows a flow chart showing an example of a series of writingoperations. The writing operation is performed when a write enablesignal (WE) is asserted (S1). When the write enable signal is asserted(S1), first, a memory cell specified by the address signal (ADR) isselected; therefore, the input data is written to the selected memorycell (S2). Then, after the input data is written, the result of thewriting is confirmed by comparing the data stored in the selected memorycell with the input data (S3). When both the data accord (S4), it isdetermined that the writing operation is performed normally; therefore,the writing operation is completed (S5). When both the data discord(S6), it is determined that abnormality is caused in the writing;therefore, the address where abnormality is caused is allocated to theredundant memory cell (S7). Then, the writing operation is completed byperforming writing again.

Note that, when the writing is determined as abnormal writing, thenumber of times that the address where abnormality is caused can beallocated to the redundant memory cell depends on the structure of theredundant memory cell, the word line driver circuit 108, or the bit linedriver circuit 107. When the address can be allocated more than once,the result of the writing may be repeatedly confirmed equivalently tothe number of times. When a writing defect is caused beyond the numberof times that the address can be allocated to the redundant memory cell,this causes defective writing. In addition, before completing a seriesof writing operations, the result of the writing may be confirmed, sothat the determination signal that notify whether the writing operationis normally completed or the defect is caused is output.

By having such a structure and performing such a writing operation, thewrite-once memory of the present invention is capable of considerablyreducing the probability of being defective. For example, given amanufacturing process having a 1-bit defect per 1G bit, a conventional1M-bit write-once memory becomes defective even in a case of a 1-bitdefect; therefore, approximately one defect is caused among 1,000write-once memories. On the other hand, when a 1M-bit write-once memoryhaving the structure of the present invention can modify, for example,the arbitrary 1-bit defect, the write-once memory becomes defective onlywhen a defective bit of 2 bits or more is caused; therefore, the defectsare reduced to approximately one defect among 1,000,000 write-oncememories.

Then, the operation of each block operation shown in FIG. 1 will beexplained. The operation conditions of the reading/writing circuit 104,the memory cell of the memory cell array 109, and the memory element ofthe memory cell may be the same as those of the write-once memoryexplained with reference to FIGS. 10A and 10B. Note that the dataregister 106 is a register where reading data, writing data, orcomparison data is stored.

The memory cell array 109 includes, as its structure, the redundantmemory cell, and the bit line driver circuit 107 and the word linedriver circuit 108 each corresponding to the redundant memory cell. Forexample, a structure where one word line and one row of the memory cellare added can be considered. The word line driver circuit 108 has anonvolatile memory element that stores setting of allocation of theaddress to the redundant memory cell. The second writing circuit 110 isa circuit that performs writing to the memory element. For example, whenabnormal writing is caused with the input address, writing is performedin the second writing circuit 110; therefore, the address is allocatedto the redundant memory cell.

The verifying circuit 105 is a circuit that compares data that performwriting with data after writing and outputs a determination signal. Forexample, the two pieces of data are compared by performing exclusive-OR,thereby generating a determination signal by obtaining OR of allcomparative results. In this case, the determination signal expressesaccordance with a logical value of “0” and discordance with a logicalvalue of “1”, thereby outputting a logic value of “0” at the time ofnormal writing and a logic value of “1” at the time of abnormal writing,respectively.

The timing control circuit 111 is a circuit that controls the timing ofa series of writing operations of the present invention. The timingcontrol circuit 111, to which the WE signal, the RE signal, the CLKsignal, and the determination signal are input, generates and outputs asignal that controls the reading/writing circuit 104, a signal thatcontrols the verifying circuit 105, and a signal that controls thesecond writing circuit 110, respectively.

The signal that controls the reading/writing circuit 104 at least has afourth control signal that controls reading and a third control signalthat controls writing, which are input to the reading/writing circuit104. The signal that controls the verifying circuit 105 (also referredto as a first control signal) is input to the verifying circuit 105. Thesignal that controls the second writing circuit 110 (also referred to asa second control signal) is input to the second writing circuit 110.

When the RE signal is asserted, the bit line driver circuit 107, theword line driver circuit 108, and a reading circuit in thereading/writing circuit 104 are enabled, so that a normal readingoperation is controlled. In addition, when the WE signal is asserted,for example, a series of writing operations as will be described belowis controlled.

When the WE signal is asserted, the bit line driver circuit 107, theword line driver circuit 108, and the writing circuit are enabled, andthe writing of the input data is performed. Next, the result of thewriting is confirmed by enabling the verifying circuit 105. Then, thefollowing process will be performed based on the determination signalwhich is output from the verifying circuit 105.

When the determination signal indicates normal writing, the writingoperation is completed. When the determination signal indicates abnormalwriting, the timing control circuit 111 makes the second writing circuit110 enable, so that the input address is allocated to the redundantmemory cell. Next, the bit line driver circuit 107, the word line drivercircuit 108, and the writing circuit in the reading/writing circuit 104(the first writing circuit) are enabled, so that the writing operationis completed after writing the input data to a memory cell which isnewly allocated. FIGS. 4A and 4B each show a timing chart at the time ofthe writing that is controlled by the timing control circuit 111. FIG.4A shows a timing chart at the time of normal writing, and FIG. 4B showsa timing chart at the time of abnormal writing.

Note that the process in the case where the determination signalindicates abnormal writing is slightly different depending on thestructure of the redundant memory cell. The above process is performedin the case of the structure where the redundant memory cell isallocated only to the address where writing is performed. On the otherhand, a case, where the redundant memory is allocated to one rowincluding the address where writing is performed, is as follows.

When the determination signal indicates abnormal writing, the timingcontrol circuit 111 makes the bit line driver circuit 107, the word linedriver circuit 108, and the reading circuit of the reading/writingcircuit 104 enable, so that reading of the data of a row where abnormalwriting is caused is performed. At this time, based on the data of a rowwhere abnormal writing is caused and the input data, the reading/writingcircuit forms the data of one row of a case, where normal writing isperformed, which is stored in the data register 106. Next, the secondwriting circuit 110 is enabled, and the input address is allocated tothe redundant memory cell. Then, the bit line driver circuit 107, theword line driver circuit 108, and the writing circuit in thereading/writing circuit 104 are enabled, so that the writing operationis completed after writing the data of one row which is stored in thedata register 106 to a memory cell which is newly allocated.

As described through the above, the timing control circuit 111 controlsthe timing of the reading operation or a series of the writingoperations.

Next, an example of the word line driver circuit 108 corresponding tothe redundant memory cell will be explained with reference to FIG. 3. Aword line driver circuit 301 shown in FIG. 3 includes a row decoder 303,a level shifter 304, a redundant row decoder 305, an active bit 306, andother logic gates, and a row address signal, a column address signal,and an enable signal are input to the word line driver circuit 301. Theenable signal and the row address signal are input to the row decoder303. When the enable signal is asserted, a word line specified by therow address is selected, and other word line is not selected. Theredundant row decoder 305 has an address register 307 where the addressof the redundant memory cell is stored, and the enable signal and theaddress signal are input thereto. Then, when the enable signal isasserted and the input address accords with the address stored in theaddress register, the word line connected to the redundant memory cellis selected. In other cases, the word line connected to the redundantmemory cell is not selected. The address register 307 and the active bit306 are each formed by a nonvolatile memory, and a 1-bit memory elementcan be used as well as the memory element included in the memory cell.In a second writing circuit 302, a control signal from the timingcontrol circuit 111 is input and written to the address register 307 andthe active bit 306 of the word line driver circuit 301.

Then, the operation of the word line driver circuit 301 shown in FIG. 3will be explained. The initial values of the address register 307 andthe active bit 306 are each assumed as a logic value of “1”, and theenable signal is assumed to be asserted at a logic value of “1”. Inaddition, among the output signals of the row decoder 303, logic valuesof “1” and “0” are assumed to be output to the signal line that isselected and the signal line that is not selected, respectively.

When the output signal of the redundant row decoder 305 is a logic valueof “0” (not selected), the enable signal input to the word line drivercircuit 301 and the enable signal input to the row decoder 303 areaccorded with each other, so that the word line driver circuit 301serves as a word line driver circuit having no redundant configuration.Therefore, when the enable signal input to the word line driver circuit301 is asserted, the row decoder 303 selects the word line specified bythe row address. On the other hand, when the output signal of theredundant row decoder 305 is a logic value of “1” (selected), the enablesignal input to the row decoder 303 is not asserted; thus, only the wordline connected to the redundant memory cell is selected.

The enable signal of the redundant row decoder 305 is not assertedbecause the active bit 306 is a logic value of “1” at the initial state,so that the word line driver circuit 301 serves as a word line drivercircuit having no redundant configuration. In other words, when theenable signal is asserted, the row decoder 303 selects the word linespecified by the row address.

Then, it is assumed that a logic value of “0” and an address to beallocated to the redundant memory cell are written to the active bit 306and the address register 307, respectively, by the second writingcircuit 302. In this case, when the enable signal input to the word linedriver circuit 301 is asserted, the enable signal input to the redundantrow decoder 305 is also asserted. Accordingly, the input address and theaddress stored in the address register 307 are compared. When both theaddresses accord, only the word line connected to the redundant memorycell is selected. When both the addresses disaccord, the word lineconnected to the redundant memory cell is not selected but the outputsignal of the redundant row decoder 305 is a logic value of “0”, so thatthe redundant row decoder 305 serves as a word line driver circuithaving no redundant configuration. Consequently, the row decoder 303selects the word line specified by the row address.

The examples shown in FIG. 3 has the structure where only the address,where abnormal writing is performed, is allocated to the redundantmemory cell by the row address and the column address stored in theaddress register 307. It is also possible to have a structure where onlythe row address is stored in the address register 307. In this case, thestructure where, the entire row specified by the row address whereabnormal writing is caused is allocated to the redundant memory cell, isobtained.

Note that the case of adding a memory corresponding to one row of theword line as the redundant memory cell is described; however, aplurality of rows can also be added. In addition, one or a plurality ofbit lines can also be added.

Next, an example of a detailed circuit configuration of the word linedriver circuit 301 shown in FIG. 3 will be explained. FIG. 5 shows partof a word line driver circuit 501 and a second writing circuit 502. InFIG. 5, the word line driver circuit 501 includes an active bit 504, aredundant row decoder 503, and a logic gate 511, to which an enablesignal and a k (k is a natural number)-bit address signal are input. Thek-bit address signal may include a row address and a column address, oronly a row address.

The active bit 504 has a select transistor 505, a memory element 506,and a pull-up resistor 507. The memory element 506, the initial state ofwhich is in high resistance, outputs a logic value of “1”. At the timeof writing, for example, a signal of 6V is input from the second writingcircuit 502, and the memory element 506 is changed into a low-resistantstate. Consequently, the resistant value of the memory element 506 getssmaller enough than that of the pull-up resistor 507, and the active bit504 outputs a logic value of “0”.

The redundant row decoder 503 includes an address register 513, acomparator 509, a logic gate 510, and a level shifter 512. The addressregister 513 includes k-bit memory cells 508 (1), and 508 (2) to 508(k), each of which has a select transistor, a memory element, and apull-up resistor. At the time of writing, the input k-bit address iswritten by inputting, for example, a signal of 6V from the secondwriting circuit 502. The comparator 509 compares an address signal andan address stored in the address register 513. The logic gate 510performs a logic operation of an enable signal input to the redundantrow decoder 503 and the output signal of the comparator 509.Consequently, a redundant word line is selected only when the enablesignal is asserted and the input address accord with the address storedin the address register 513.

By having such a structure and performing such a writing operation, thewrite-once memory of the present invention is capable of considerablyreducing the probability of being defective.

Note that this embodiment mode explains the case where the memoryelement is in high resistance at the initial state and in low resistanceafter the writing; however, the element characteristics of the memoryelement is not limited thereto. The memory element may havecharacteristics that the initial state is in low resistance, which ischanged into high resistance with a voltage applied. In addition, otherthan the element, the characteristics of which are changed due to theapplication of a voltage, an element, the characteristics of which arechanged with a current applied, may also be used.

Note that, in the structure shown in this embodiment mode, the bit widthfor performing writing or reading is not particularly specified. Serialwriting and serial reading per 1 bit, synchronizing writing andsynchronizing reading of a plurality of bits, one-line row simultaneousreading and one-line row simultaneous writing, or one-line rowsimultaneous reading and serial writing may be combined.

Embodiment 1

The structure and operation of a write-once memory of the presentinvention will be explained by giving an example different from FIG. 1.FIG. 6 is a block diagram of the write-once memory of the presentinvention, where a memory 601 includes a reading circuit 603 having adata register 602, a writing circuit 605 having a data register 604(also referred to as a first writing circuit), a verifying circuit 606,a timing control circuit 607, a second writing circuit 608, an addressregister 609, a bit line driver circuit 610, a word line driver circuit611, a memory cell array 612, and a boosting circuit 613. In addition, awrite enable signal (WE), a read enable signal (RE), a clock signal(CLK), an address signal (ADR), an input data signal (DATAIN), and asecond clock signal (CLK2) are input to the memory 601, and an outputdata signal (DATAOUT) is output.

As compared with the block diagram shown in FIG. 1, FIG. 6 includes theboosting circuit 613 and the address register 609 and shows an exampleof a diagram of a reading/writing/verifying circuit (corresponding tothe reading circuit 603, the writing circuit 605, and the verifyingcircuit 606 in FIG. 6), the bit line driver circuit 610, and the wordline driver circuit 611.

The reading circuit 603 and the writing circuit 605 each have a dataregister. The data read by the reading circuit 603 is stored in the dataregister 602, and the input data written by the writing circuit 605 isstored in the data register 604. The verifying circuit 606 refers to thedata of the reading circuit 603 that is stored in the data register 602and the data of the writing circuit 605 that is stored in the dataregister 604, and the two pieces of data are compared.

The bit line driver circuit 610 includes a column decoder 614, a levelshifter 615, and a selector 616. A column address is input to the columndecoder 614 from the address register 609, and decoding is performed. Inthe level shifter 615, the level of the output potential of the columndecoder 614 is shifted. For example, at the time of writing, the outputof the column decoder, the voltage of which is 0 to 3V, is converted toa high voltage of 0 to 6V. The selector 616 performs switching inaccordance with the output of the level shifter 615, and the bit linespecified by the column address is connected to the reading circuit 603or the writing circuit 605. The word line driver circuit 611 includes arow decoder 617 and a level shifter 618. In the row decoder 617, towhich the row address signal is input from the address register,decoding is performed. In the level shifter 618, the level of the outputpotential of the row decoder is shifted, so that the word line isdriven.

In the boosting circuit 613, to which the second clock signal and acontrol signal from the timing control circuit 607 are input, a highpower supply voltage which is necessary at the time of writing isgenerated, and the high power supply voltage is provided to the levelshifter 615, the level shifter 618, and the writing circuit 605.

The timing control circuit 607 controls the timing of the readingcircuit 603, the writing circuit 605, the verifying circuit 606, thesecond writing circuit 608, the bit line driver circuit 610, the wordline driver circuit 611, and the boosting circuit 613. In addition, adetermination signal output from the verifying circuit 606 is input tothe timing control circuit 607.

Other structures and operations are the same as those of FIG. 1. Thememory cell array 612 includes a redundant memory cell and a drivercircuit having a structure corresponding to the redundant memory cell.When the read enable signal (RE) is asserted, the memory cell specifiedby the address signal is selected; therefore, the data stored in theselected memory cell is read as the output data signal (DATAOUT). Inaddition, when the write enable signal is asserted, the memory cellspecified by the address signal is selected; therefore, the input datais written to the selected memory cell. Then, after the input data iswritten, the written data and the input data are compared. When the twopieces of data discord, the address input to the redundant memory cellis allocated, so that the writing is performed again.

By having such a structure and performing such a writing operation, thewrite-once memory of the present invention is capable of considerablyreducing the probability of being defective.

Note that, in the structure shown in this embodiment, the bit width forperforming writing or reading is not particularly specified. Serialwriting and serial reading per 1 bit, synchronizing writing andsynchronizing reading of a plurality of bits, one-line row simultaneousreading and one-line row simultaneous writing, or one-line rowsimultaneous reading and serial writing may be combined. This embodimentcan be implemented by being arbitrarily combined with Embodiment Modedescribed above.

Embodiment 2

An example of a circuit configuration, which differs from that of FIG.3, of a word line driver circuit and a second writing circuit will beexplained.

FIG. 7 shows a word line driver circuit 701 and a second writing circuit702. The word line driver circuit 701 includes in its structure a rowdecoder 703, a level shifter 704, a set bit 705, logic gates 710 (1) to710 (n−1), transmission gates 711 (1) to 711 (n) and 712 (1) to 712 (n),and inverters 713 (1) to 713 (n). A row address and an enable signal areinput to the word line driver circuit 701, and word lines W1 to W (n+1)are output. The number of output signals of the row decoder 703 is n,whereas the number of word lines is (n+1) including one word lineconnected to the redundant memory cell.

The set bit 705 is provided with a memory cell 706 (i) (i=1 to n) forevery output of the row decoder 703. The set bit 705 is a nonvolatilememory, and a memory cell the same as that of the memory cell array canbe used. Each memory cell 706 (i) includes a select transistor 707 (i),a pull-up resistor 708 (i), and a memory element 709 (i) (i=1 to n). Atthe initial state, the memory element is in a state of high resistance,and data, the logic value of which is “1”, is output. At the time ofwriting, the memory element of the row specified by the input address ischanged to a state of low resistance by inputting, for example, acontrol signal of approximately 6V from the second writing circuit 702.Consequently, the resistance of the memory element gets lower than thatof the pull-up resistor by enough, so that data, the logic value ofwhich is “0”, is written.

The output signal out (i) of the level shifter 704 is connected throughthe word line W (i) and the transmission gate 711 (i) and through theword line W (i+1) and the transmission gate 712 (i) (i=1 to n). Thetransmission gates 711 (i) and 712 (i) are controlled by the outputsignals of the set bit at 1 to i rows.

The control signal from the timing control circuit is input to thesecond writing circuit 702, and the second writing circuit 702 outputsthe control signal to the level shifter 704 and the set bit 705.

Next, the operation of the word line driver circuit 701 will beexplained. The initial value of the set bit 705 is to be a logic valueof “1”, and a logic value of “1” is to be output when the word line isselected and a logic value of “0” is to be output when the word line isnot selected.

Since the set bit is a logic value of “1” at the initial state, all ofthe transmission gates 711 (i) are turned on, and all of thetransmission gates 712 (i) are turned off. Thus, the output signal out(i) of the level shifter is connected to the word line W (i), and theword line W (i) is driven. The word line W (n+1) is not used.

Then, it is assumed that a logic value of “0” is written to the k-th rowset bit only by the second writing circuit 702. In this case, the outputof the memory cell 706 (k) is a logic value of “0”. As for the k-th rowor thereafter, all of the transmission gates 711 (i) (i=k to n) areturned off, and all of the transmission gates 712 (i) (i=k to n) areturned on. On the other hand, since the set bit of the 1st to (k−1)-throws is a logic value of “1”, all of the transmission gates 711 (i) (i=1to (k−1)) are turned on, and all of the transmission gates 712 (i) (i=1to (k−1)) are turned off. Therefore, when i=1 to (k−1) is set, theoutput signal out (i) of the level shifter is connected to the word lineW (i), and the word line W (i) is driven. On the other hand, when i=k ton is set, the output is connected to the word line W (i+1), and the wordline W (i+1) is driven. The word line W (k) is not used.

In such a manner, it is found that the word line driver circuit 701shown in FIG. 7 can modify an arbitrary row. In other words, whenabnormal writing occurs at the k-th row, a logic value of “0” is writtento the k-th row set bit, so that the use of the k-th row is canceled,and the row address can be allocated with all lines shifted by one.

Note that, when the redundant memory having such a structure is used forthe write-once memory of the present invention, it is necessary thatwriting to a memory not be performed through random access but beperformed sequentially.

This embodiment can be implemented by being arbitrarily combined withEmbodiment Mode and Embodiment 1 described above.

Embodiment 3

An example of the structure of the verifying circuit will be explainedwith reference to FIG. 8.

FIG. 8 shows an example of a structure of a writing circuit 801, areading circuit 802, and a verifying circuit 803 when the data bit widthis 4 bits. The writing circuit 801 includes a data register 804 whereinput data (DATAIN) and a control signal are input and the value of thedata register 804 is output. The reading circuit 802 includes a senseamplifier 806 and a data register 805 where the data output from the bitline driver circuit and a control signal are input and the value of thedata register 805 is output. The verifying circuit 803 includes anexclusive-OR gate and an OR gate where the control signal and the valuesof the data register 804 and the data register 805 are input so that adetermination signal is output.

The verifying circuit 803 shown in FIG. 8 performs exclusive-ORoperations for each bit of the data register 804 and the data register805. Then, a determination signal is generated by performing an ORoperation for each operation result. The determination signal is a logicvalue of “0” only when the data register 804 and the data register 805are in complete accordance with each other, and the determination signalis a logic value of “1” when the two registers are in discordance byeven 1 bit.

As shown in FIG. 8, when the verifying circuit 803 includes onlycombinational circuits, it is not necessary to input a control signalfrom the timing control circuit. On the other hand, when a latch isprovided at the output of the OR gate, the value of the determinationsignal is updated through synchronization with the control signal. Whensuch timing control is performed, the control signal is necessary.

Note that this embodiment can be implemented by being arbitrarilycombined with Embodiment Mode and Embodiments 1 and 2 described above.

Embodiment 4

As an application mode of the write-once memory of the presentinvention, a mode in which a semiconductor device having a wirelesscommunication function is incorporated will be explained. Such asemiconductor device is used, for example, as an RFID tag (radiofrequency identification). FIG. 9 shows an example of a block diagram ofthe semiconductor device.

FIG. 9 shows an RFID tag including an antenna 901 and a semiconductordevice 902. It may be considered that the antenna is included in thesemiconductor device.

The semiconductor device 902 includes a matching circuit 903, amodulation circuit 904, a demodulation circuit 905, a power supplycircuit 906, a phase locked loop 907, and a logic circuit portion 908.The logic circuit portion 908 includes part of an antenna circuit.However, in many cases, the logic circuit portion 908 is composed oflogic circuits and is a portion that determines the function of thesemiconductor device.

The logic circuit portion 908 includes a decoding circuit 909, anencoding circuit 910, instruction decoder 911, a check circuit 912, anoutput control circuit 913, a memory control circuit 914, a ROM 915, awrite-once memory 916, and a boosting circuit 917.

The matching circuit 903, which is a circuit for obtaining matching ofthe semiconductor device 902 and the antenna 901, is provided, ifnecessary. The modulation circuit 904, having a load resistor and aswitching element, is a circuit for changing the impedance of a tag inaccordance with an input signal. The demodulation circuit 905, which hasan envelope circuit, is a circuit for extracting a sub-carrier wave fromthe received electromagnetic wave. The power supply potential Vdd of thepower supply circuit 906, which has a rectifier circuit, a storagecapacitor, and a constant voltage circuit, is supplied to the logiccircuit portion 908 and the phase locked loop 907. The phase locked loop907, having a loop filter, a VCO (Voltage Controlled Oscillator), and afrequency dividing circuit, generates a clock signal based on the inputof the sub-carrier wave.

The ROM 915 is a read-only-memory for storing identification numbers andvarious fixed information. A mask ROM or the like can be used. Thewrite-once memory of the present invention is used for the write-oncememory 916. By incorporating the write-once memory, data can be addedafter shipping; therefore, historical information or the like of anobject can be made clear by non-contact so as to be of use formanufacturing, management, or the like.

The decoding circuit 909 performs decoding in accordance with thestandards of a coded digital signal that is output from the demodulationcircuit. The instruction decoder 911 decodes instructions from thedecoded signal and outputs various control signals in accordance withdata comparison, state changes, and instructions. In addition, the dataread from the ROM 915 or the write-once memory is input or the data tobe written to the write-once memory is output. The memory controlcircuit 914, to which the control signal is input, generates apredetermined address, and reading of the ROM 915 or reading or writingof the write-once memory 916 is controlled. The boosting circuit 917which is necessary at the time of writing of the write-once memory 916is also controlled.

The output control circuit 913, to which the control signal from theinstruction decoder 911 is input, prepares data to be output andperforms timing control. The control signal is output to the memorycontrol circuit 914, and the data read from the ROM 915 or thewrite-once memory is input. The logic circuit portion 908 may have arandom number generation circuit that determines a time slot to beoutput. The check circuit 912, including a CRC (Cyclic Redundancy Check)circuit or a parity check circuit, to which the output signal from theencoding circuit 910 is input, checks whether the receive data istransferred accurately. Moreover, the input signal from the encodingcircuit 910 is input, and data capable of checking whether transmit datais transferred accurately is generated. The encoding circuit 910 encodesthe data output from the output control circuit 913 in accordance withthe standards.

By having such a structure, the semiconductor device in which thewrite-once memory of the present invention is incorporated can berealized. Such a semiconductor device of the present invention can beused for an RFID tag, for example. By using the semiconductor device ofthe present invention, data can be added; therefore, historicalinformation or the like of an object can be made clear by non-contact soas to be of use for manufacturing, management, or the like. Moreover,since there are few defects and data is not rewritten, a high level ofsecurity is realized.

Further, in the semiconductor device of the present invention, it ispreferable to mount an organic write-once memory capable of being formedthrough a low temperature process. Since the organic write-once memorycan be manufactured through a low temperature process, the memory can beformed over a flexible substrate and an application mode thereof as anRFID tag is expanded remarkably.

Note that this embodiment can be implemented by being arbitrarilycombined with Embodiment Mode and Embodiments 1 to 3 described above.

Embodiment 5

This embodiment will explain a method for manufacturing the write-oncememory of the present invention using an organic memory element over aflexible substrate with reference to FIGS. 11A and 11B and FIGS. 12A and12B.

As shown in FIGS. 11A and 11B, a peeling layer 268 and an insulatinglayer 251 are formed over a substrate 250. Over the insulating layer251, a transistor 260 a and a transistor 260 b are formed. Each of thetransistors 260 a and 260 b in FIGS. 11A and 11B is a top-gate planarthin film transistor in which a sidewall is provided on an end portionof a gate electrode layer; however, the present invention is not limitedto this structure. Over the transistors 260 a and 260 b, an insulatinglayer 269 and an insulating layer 261 are stacked. In the insulatinglayers 269 and 261, openings reaching each of impurity regions which aresource regions and drain regions in semiconductor layers of thetransistors 260 a and 260 b are formed. In the openings, a wiring layer255 a, a wiring layer 255 b, a wiring layer 255 c, and a wiring layer255 d are formed.

An insulating layer 270 is formed over the wiring layers 255 a, 255 b,255 c, and 255 d. In the insulating layer 270, openings each reachingthe wiring layers 255 a and 255 c are formed. A first conductive layer256 a and a first conductive layer 256 b are formed in the openings, andthe first conductive layer 256 a and the first conductive layer 256 bare electrically connected to the transistor 260 a and the transistor260 b through the wiring layer 255 a and the wiring layer 255 c,respectively.

A partition (an insulating layer) 267 is formed which has openings overthe first conductive layer 256 a and the first conductive layer 256 band covers end portions of the first conductive layers 256 a and 256 b.An organic compound layer 262 a is stacked over the first conductivelayer 256 a, while an organic compound layer 262 b is stacked over thefirst conductive layer 256 b, and a second conductive layer 263 isformed over the organic compound layers 262 a and 262 b and thepartition (insulating layer) 267 (see FIG. 11A). In this manner, amemory element 265 a including the first conductive layer 256 a, theorganic compound layer 262 a, and the second conductive layer 263, and amemory element 265 b including the first conductive layer 256 b, theorganic compound layer 262 b, and the second conductive layer 263 areprovided over the substrate 250.

As the substrate 250, a glass substrate made of barium borosilicateglass, alumino borosilicate glass, or the like; a quartz substrate; ametal substrate or a stainless-steel substrate having an insulatinglayer over a surface thereof; or a plastic substrate which can withstandthe process temperature of the manufacturing process in this embodimentmode is used. The surface of the substrate 250 may be polished by a CMPmethod or the like so as to be planarized.

The peeling layer 268 is formed by a sputtering method, a plasma CVDmethod, a coating method, a printing method, or the like, using a singlelayer or a multi-layer of a layer formed of an element of tungsten (W),molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel(Ni), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium(Rh), palladium (Pd), osmium (Os), iridium (Ir), and silicon (Si); or analloy material or a compound material containing any of the elements asits main component. A layer containing silicon may have any of anamorphous structure, a microcrystalline structure, or a polycrystallinestructure. Note that a coating method includes a spin-coating method, adroplet discharge method, and a dispensing method in its category here.

In a case where the peeling layer 268 has a single-layer structure, atungsten layer, a molybdenum layer, or a layer containing a mixture oftungsten and molybdenum is preferably formed. Alternatively, a layercontaining oxide or oxynitride of tungsten, a layer containing oxide oroxynitride of molybdenum, or a layer containing oxide or oxynitride of amixture of tungsten and molybdenum is formed. Note that the mixture oftungsten and molybdenum corresponds to, for example, an alloy oftungsten and molybdenum.

In a case where the peeling layer 268 has a multi-layer structure,preferably, a tungsten layer, a molybdenum layer, or a layer containinga mixture of tungsten and molybdenum is formed as the first layerthereof, and a layer containing tungsten, molybdenum, or oxide, nitride,oxynitride or nitride oxide of a mixture of tungsten and molybdenum isformed as the second layer thereof.

In the case where the peeling layer 268 has a multi-layer structure of alayer containing tungsten and a layer containing tungsten oxide, thelayer containing tungsten may be formed first and an insulating layerformed of oxide may be formed over the layer containing tungsten so thata layer containing tungsten oxide can be formed at an interface betweenthe tungsten layer and the insulating layer. Alternatively, thermaloxidization treatment, oxygen plasma treatment, or treatment with asolution having strong oxidizability such as ozone water may beperformed to a surface of a layer containing tungsten so that a layercontaining tungsten oxide is formed; the plasma treatment or the thermaltreatment may be performed in an atmosphere of oxygen, nitrogen,dinitrogen monoxide, an elementary substance of dinitrogen monoxide, ora mixed gas of the gas and another gas. The same can be applied to acase of forming a layer containing a nitride, an oxynitride, or anitride oxide of tungsten over a layer containing tungsten; afterforming the layer containing tungsten, a silicon nitride layer, asilicon oxynitride layer, or a silicon nitride oxide layer is preferablyformed.

Tungsten oxide is denoted by WOx. The “x” is within the range of 2 to 3,and there are WO₂ (where x is 2), W₂O₅ (where x is 2.5), W₄O₁₁ (where xis 2.75), WO₃ (where x is 3), or the like.

Further, although the peeling layer 268 is formed so as to be in contactwith the substrate 250 in the above process, the present invention isnot limited to this process. An insulating layer which is a base may beformed so as to be in contact with the substrate 250, and the peelinglayer 268 may be formed so as to be in contact with the insulatinglayer.

The insulating layer 251 is formed using an inorganic compound with asingle-layer structure or a multi-layer structure by a sputteringmethod, a plasma CVD method, a coating method, a printing method, or thelike. As a typical example of the inorganic compound, there is oxide ofsilicon or nitride of silicon. As a typical example of oxide of silicon,there is silicon oxide, silicon oxynitride, silicon nitride oxide, orthe like. As a typical example of nitride of silicon, there is siliconnitride, silicon oxynitride, silicon nitride oxide, or the like.

Moreover, the insulating layer 251 may have a multi-layer structure. Forexample, a multi-layer may be formed by using an inorganic compound;typically, silicon oxide, silicon nitride oxide, and silicon oxynitridemay be stacked.

As a material for forming the semiconductor layer included in thetransistors 260 a and 260 b, an amorphous semiconductor (hereinafteralso referred to as an “AS”) manufactured using a semiconductor materialgas typified by silane or germane by a vapor phase growth method or asputtering method; a polycrystalline semiconductor that is formed bycrystallizing the amorphous semiconductor by utilizing light energy orthermal energy; a semi-amorphous (also referred to as microcrystallineor microcrystal) semiconductor (hereinafter also referred to a “SAS”);or the like can be used. The semiconductor layer can be formed by aknown method (a sputtering method, a LPCVD method, a plasma CVD method,or the like).

SAS is a semiconductor having an intermediate structure between anamorphous structure and a crystalline (including a single crystal and apolycrystal) structure and having a third state which is stable in freeenergy, and contains a crystalline region having short-range order andlattice distortion. The SAS is formed by glow discharge decomposition(plasma CVD) of a gas containing silicon. As the gas containing silicon,Si₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄, SiF₄, or the like, as well as SiH₄, canbe used. Further, F₂ or GeF₄ may be mixed into the above gas containingsilicon. This gas containing silicon may be diluted with H₂, or H₂ andone or more rare gas elements of He, Ar, Kr, and Ne. Further, as thesemiconductor layer, an SAS layer formed using a hydrogen-based gas maybe stacked over a SAS layer formed using a fluorine-based gas.

The amorphous semiconductor is typified by hydrogenated amorphoussilicon, and the crystalline semiconductor is typified by polysilicon orthe like. Polysilicon (polycrystalline silicon) includes so-calledhigh-temperature polysilicon which contains polysilicon that is formedat a process temperature of 800° C. or more as its main component,so-called low-temperature polysilicon which contains polysilicon that isformed at a process temperature of 600° C. or less as its maincomponent, polysilicon which is crystallized by adding an element forpromoting crystallization, or the like in its category. As describedabove, of course, either a semiconductor which contains a crystallinephase in a portion of the semiconductor layer or a semi-amorphoussemiconductor can also be used.

Moreover, as a material of the semiconductor, a compound semiconductorsuch as GaAs, InP, SiC, ZnSe, GaN, or SiGe can be used as well as anelementary substance such as silicon (Si) or germanium (Ge). Further, anoxide semiconductor such as zinc oxide (ZnO) or tin oxide (SnO₂) canalso be used; in the case of using ZnO for the semiconductor layer, thegate insulating layer may be formed of Y₂O₃, Al₂O₃, TiO₂, a multi-layerthereof, or the like, and the gate electrode layer, the source electrodelayer, and the drain electrode layer may be formed of ITO (Indium TinOxide), Au, Ti, or the like. In addition, In, Ga, or the like can alsobe added to ZnO.

In a case where a crystalline semiconductor layer is used as thesemiconductor layer, a known method (a laser crystallization method, athermal crystallization method, a thermal crystallization method usingan element for promoting crystallization such as nickel, or the like)may be employed as a manufacturing method of the crystallinesemiconductor layer. Alternatively, a microcrystalline semiconductorwhich is a SAS can be crystallized by laser irradiation to improve thecrystallinity. In a case where the element for promoting crystallizationis not introduced, hydrogen is released until the concentration ofhydrogen contained in an amorphous silicon film becomes less than orequal to 1×10²⁰ atoms/cm³ by heating the amorphous silicon film at atemperature of 500° C. for an hour in a nitrogen atmosphere beforeirradiating the amorphous silicon film with laser light. This is becausethe amorphous silicon film containing much hydrogen is damaged when thefilm is irradiated with laser light.

Any method can be used for introducing a metal element to the amorphoussemiconductor layer as long as the metal element can exist on a surfaceof or inside the amorphous semiconductor layer. For example, asputtering method, a CVD method, a plasma treatment method (including aplasma CVD method), an adsorption method, or a method of coating a metalsalt solution can be employed. Among them, the method using a solutionis simple, easy, and advantageous in easy control of the concentrationof the metal element. In addition, at this time, it is preferable toform an oxide film by UV light irradiation in an oxygen atmosphere, athermal oxidation method, treatment with ozone water including ahydroxyl radical, or hydrogen peroxide, or the like in order to improvewettability of the surface of the amorphous semiconductor layer and tospread the aqueous solution over the entire surface of the amorphoussemiconductor layer.

Further, at the crystallization step for forming a crystallinesemiconductor layer by crystallizing the amorphous semiconductor layer,an element (also referred to as a catalytic element or a metal element)which promotes crystallization may be added to the amorphoussemiconductor layer, and heat treatment (at temperatures from 550° C. to750° C. for 3 minutes to 24 hours) may be performed for crystallization.As the metal element which promotes crystallization, one kind or pluralkinds of metal elements of iron (Fe), nickel (Ni), cobalt (Co),ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir),platinum (Pt), copper (Cu), and gold (Au) can be used.

In order to remove or reduce the element which promotes crystallizationfrom the crystalline semiconductor layer, a semiconductor layercontaining an impurity element is formed in contact with the crystallinesemiconductor layer, and the semiconductor layer functions as agettering sink. As the impurity element, an impurity element impartingn-type conductivity, an impurity element imparting p-type conductivity,a rare gas element, or the like can be used; for example, one kind orplural kinds of elements of phosphorus (P), nitrogen (N), arsenic (As),antimony (Sb), bismuth (Bi), boron (B), helium (He), neon (Ne), argon(Ar), krypton (Kr), and xenon (Xe) can be used. The semiconductor layercontaining a rare gas element is formed over the crystallinesemiconductor layer containing the element which promotescrystallization, and heat treatment (at temperatures from 550° C. to750° C. for 3 minutes to 24 hours) is performed. The element whichpromotes crystallization in the crystalline semiconductor layer movesinto the semiconductor layer containing the rare gas element, so thatthe element which promotes crystallization in the crystallinesemiconductor layer is removed or reduced. Thereafter, the semiconductorlayer containing the rare gas element, which functions as the getteringsink, is removed.

Heat treatment and laser light irradiation may be combined tocrystallize the amorphous semiconductor layer. Alternatively, only oneof heat treatment and laser light irradiation may be performed pluraltimes.

Moreover, a crystalline semiconductor layer may be directly formed onthe substrate by a plasma method as well. Alternatively, a crystallinesemiconductor layer may be selectively formed over the substrate by aplasma method.

The semiconductor layer can be formed using an organic semiconductormaterial by a printing method, a spray method, a spin-coating method, adroplet discharge method, or the like. In this case, since the aboveetching step is not required, the number of steps can be reduced. Alow-molecular material, a high-molecular material, or the like is usedas the organic semiconductor material, and a material such as an organicpigment or a conductive high-molecular material can be used as well. Aπ-electron conjugated high-molecular material having a skeletonincluding conjugated double bonds is preferably used as the organicsemiconductor material. Typically, a soluble high-molecular materialsuch as polythiophene, polyfluorene, poly(3-alkylthiophene), apolythiophene derivative, or pentacene can be used.

As well as the above, there is a material which can form thesemiconductor layer by processing after the deposition of a solubleprecursor, as the organic semiconductor material applicable to thepresent invention. As such an organic semiconductor material, there ispolythienylenevinylene, poly(2,5-thienylenevinylene), polyacetyrene, apolyacetyrene derivative, polyarylenevinylene, or the like.

For converting the precursor to an organic semiconductor, a reactioncatalyst such as a hydrogen chloride gas is added in addition to heattreatment. The following can be employed as a typical solvent whichdissolves the soluble organic semiconductor material: toluene, xylene,chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane,γ-butyrlactone, butyl cellosolve, cyclohexane, NMP(N-methyl-2-pyrrolidone), cyclohexanone,2-butanone, dioxane,dimethylformamide (DMF), THF (tetrahydrofuran), or the like.

The gate electrode layer can be formed by a CVD method, a sputteringmethod, a droplet discharge method, or the like. The gate electrodelayer may be formed of an element of Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W,Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, and Ba; or an alloy material ora compound material containing any of the elements as its maincomponent. Moreover, a semiconductor film which is typified by apolycrystalline silicon film doped with an impurity element such asphosphorous, or an AgPdCu alloy may be used as well. Further, either asingle-layer structure or a multi-layer structure may be employed; forexample, a two-layer structure of a tungsten nitride film and amolybdenum film may be employed or a three-layer structure in which atungsten film with a thickness of 50 nm, a film of an aluminum-siliconalloy (Al—Si) with a thickness of 500 nm, or a titanium nitride filmwith a thickness of 30 nm are stacked in this order may be employed. Inthe case of employing a three-layer structure, tungsten nitride may beused instead of the tungsten for the first conductive film, a film of analuminum-titanium alloy (Al—Ti) may be used instead of the film of analuminum-silicon alloy (Al—Si) for the second conductive film, and atitanium film may be used instead of the titanium nitride film for thethird conductive film.

A light-transmitting material having a transmitting property to visiblelight can also be used for the gate electrode layer. As thelight-transmitting conductive material, indium tin oxide (ITO), indiumtin oxide containing silicon oxide (ITSO), organic indium, organic tin,zinc oxide (ZnO), or the like can be used. Moreover, indium zinc oxide(IZO) containing zinc oxide (ZnO), ZnO doped with gallium (Ga), tinoxide (SnO₂), indium oxide containing tungsten oxide, indium zinc oxidecontaining tungsten oxide, indium oxide containing titanium oxide,indium tin oxide containing titanium oxide, or the like may be used aswell.

When etching processing is required to form the gate electrode layer, amask may be formed and dry etching or wet etching may be performed. Theelectrode layer can be etched into a tapered shape by using an ICP(Inductively Coupled Plasma) etching method and appropriately adjustingthe etching condition (the amount of electric power applied to a coiledelectrode, the amount of electric power applied to an electrode on asubstrate side, the temperature of the electrode on the substrate side,or the like). As the etching gas, a chlorine-based gas typified by Cl₂,BCl₃, SiCl₄, CCl₄, or the like; a fluorine-based gas typified by CF₄,SF₆, NF₃, or the like; or O₂ can be appropriately used.

Although the explanation is made of a single gate structure in thisembodiment, a multi-gate structure such as a double-gate structure mayalso be employed. In this case, gate electrode layers may be providedabove and below the semiconductor layer or a plurality of gate electrodelayers may be provided only one side of (that is, above or below) thesemiconductor layer. The semiconductor layer may include impurityregions having different concentrations; for example, a region where thegate electrode layer is stacked in the vicinity of a channel region ofthe semiconductor layer may be formed to be a low-concentration impurityregion, while a region outside the low-concentration impurity region maybe formed to be a high-concentration impurity region.

The wiring layers 255 a, 255 b, 255 c, and 255 d can be formed byforming a conductive layer by a PVD method, a CVD method, an evaporationmethod, or the like and then etching the conductive layer into a desiredshape. In addition, the source electrode layer or the drain electrodelayer can be formed selectively in a predetermined position by aprinting method, an electric field plating method, or the like.Moreover, a reflow method or a damascene method may also be used. As amaterial of the source electrode layer or the drain electrode layer, ametal such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe,Ti, Zr, or Ba, a semiconductor such as Si or Ge, or an alloy or anitride thereof can be used. Further, a light-transmitting material canalso be used.

As the light-transmitting conductive material, indium tin oxide (ITO),indium tin oxide containing silicon oxide (ITSO), indium zinc oxide(IZO) containing zinc oxide (ZnO), zinc oxide (ZnO), ZnO doped withgallium (Ga), tin oxide (SnO₂), indium oxide containing tungsten oxide,indium zinc oxide containing tungsten oxide, indium oxide containingtitanium oxide, indium tin oxide containing titanium oxide, or the likecan be used.

The insulating layer 261, the insulating layer 270, and the partition(insulating layer) 267 may be formed of the following: an inorganicinsulating material such as silicon oxide, silicon nitride, siliconoxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride;acrylic acid, methacrylic acid, or a derivative thereof; aheat-resistant high molecule such as polyimide, aromatic polyamide, orpolybenzimidazole; or a resin material such as a vinyl resin such aspolyvinyl alcohol or polyvinyl butyral, an epoxy resin, a phenol resin,a novolac resin, an acrylic resin, a melamine resin, an urethane resin,or a siloxane resin. The acrylic or the polyimide may be either aphotosensitive material or a non-photosensitive material. In particular,the partition (insulating layer) 267 is preferably formed into a shapewhere the curvature radius is continuously changed, so that coverage ofthe organic compound layers 262 a and 262 b and the second conductivelayer 263 which are formed over the partition (insulating layer) 267 isimproved. The insulating layer can be formed by a CVD method, a plasmaCVD method, a sputtering method, a droplet discharge method, a printingmethod (a method such as screen printing, offset printing, reliefprinting, or gravure (intaglio) printing), a coating method such as spincoating, a dipping method, or the like.

In this embodiment, as a metal material used for the first conductivelayers 256 a and 256 b, and the second conductive layer 263, one kind orplural kinds of the following are used: indium (In), tin (Sn), lead(Pb), bismuth (Bi), calcium (Ca), antimony (Sb), and zinc (Zn). Further,one kind or plural kinds of the following are used as well: magnesium(Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), andbarium (Ba). A plurality of the above metal materials may be contained,or an alloy containing one kind or plural kinds of the above materialsmay be used. In particular, a metal having relatively small solubilityparameter, that is, indium (In), tin (Sn), lead (Pb), bismuth (Bi),calcium (Ca), manganese (Mn), or zinc (Zn), or an alloy containing theabove metal is suitable as an electrode material. As the alloy capableof being used, there is an indium alloy such as an indium-tin alloy(InSn), a magnesium-indium alloy (InMg), an indium-phosphorus alloy(InP), an indium-arsenic alloy (InAs), or indium-chromium alloy (InCr).

As the organic compound layers 262 a and 262 b, the following can beused: polyimide, acrylic, polyamide, benzocyclobutene, polyester, anovolac resin, a melamine resin, a phenol resin, an epoxy resin, asilicon resin, a furan resin, a diallyl phthalate resin, or a siloxaneresin.

As another organic compound that can be used for the organic compoundlayers 262 a and 262 b, the following can be used: an aromatic aminecompound (namely, a compound having a bond of a benzene ring andnitrogen) such as 4,4′-bis[N-(1-napthyl)-N-phenylamino]-biphenyl(abbreviation: α-NPD),4,4′-bis[N-(3-methylphenyl)-N-phenyl-amino]-biphenyl (abbreviation:TPD), 4,4′,4″-tris(N,N-diphenyl-amino)-triphenylamine (abbreviation:TDATA), 4,4′,4″-tris[N-(3-methylphenyl)-N-phenyl-amino]-triphenylamine(abbreviation: MTDATA), or4,4′-bis(N-(4-(N,N-di-m-tolylamino)phenyl)-N-phenylamino)biphenyl(abbreviation: DNTPD); a phthalocyanine compound such as phthalocyanine(abbreviation: H₂Pc), copper phthalocyanine (abbreviation: CuPc), orvanadyl phthalocyanine (abbreviation: VOPc); 2Me-TPD; FTPD; TPAC; OTPAC;Diamine; PDA; triphenylmethane (abbreviation: TPM); STB; or the like.

As another organic compound that can be used for the organic compoundlayers 262 a and 262 b, the following can be used: a material made of ametal complex or the like having a quinoline skeleton or abenzoquinoline skeleton such as tris(8-quinolinolato)aluminum(abbreviation: Alq₃), tris(4-methyl-8-quinolinolato)aluminum(abbreviation: Almq₃), bis(10-hydroxybenzo[h]-quinolinato)beryllium(abbreviation: BeBq₂), Orbis(2-methyl-8-quinolinolato)-4-phenylphenolato-aluminum (abbreviation:BAlq); a material made of a metal complex or the like having an oxazolebased or thiazole based ligand such asbis[2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: Zn(BOX)₂), orbis[2-(2-hydroxyphenyl)benzothiazolato]zinc (abbreviation: Zn(BTZ)₂);2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (abbreviation:PBD); 1,3-bis[5-(p-tert-butylphenyl)-1,3,4-oxadiazol-2-yl]benzene(abbreviation: OXD-7);3-(4-tert-butylphenyl)-4-phenyl-5-(4-biphenylyl)-1,2,4-triazole(abbreviation: TAZ);3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5-(4-biphenylyl)-1,2,4-triazole(abbreviation: p-EtTAZ); bathophenanthroline (abbreviation: BPhen);bathocuproin (abbreviation: BCP); 5,6,11,12-tetraphenyltetracene(abbreviation: rubrene); hexaphenylbenzene; t-butylperylene;9,10-di(phenyl)anthracene; coumarin 545T; dendrimer;4-dicyanomethylene-2-methyl-6-[2(1,1,7,7-tetramethyl-9-julolidyl)ethenyl]-4H-pyran(abbreviation: DCJT);4-dicyanomethylene-2-t-butyl-6-[2-(1,1,7,7-tetramethyljulolidin-9-yl)ethenyl]-4H-pyran(abbreviation: DCJTB); periflanthene;2,5-dicyano-1,4-bis[2-(10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl)pethenyl]benzene;N,N′-dimethylquinacridone (abbreviation: DMQd); coumarin 6;9,9′-bianthryl; 9,10-diphenylanthracene (abbreviation: DPA);9,10-bis(2-naphthyl)anthracene (abbreviation: DNA);2,5,8,11-tetra-t-butylperylene (abbreviation: TBP); BMD; BDD;2,5-bis(1-naphthyl)-1,3,4-oxadiazol (abbreviation: BND); BAPD; BBOT;TPQ1; TPQ2; MBDQ; or the like.

As another organic compound that can be used for the organic compoundlayers 262 a and 262 b, polyacetylene, polyphenylenevinylene,polythiophene, polyaniline, polyphenyleneethynylene, or the like can beused. Polyparaphenylenvinylene includes in its category a derivative ofpoly(paraphenylenvinylene) [PPV],poly(2,5-dialkoxy-1,4-phenylenevinylene) [RO-PPV],poly(2-(2′-ethyl-hexoxy)-5-methoxy-1,4-phenylenevinylene) [MEH-PPV],poly(2-(dialkoxyphenyl)-1,4-phenylenevinylene) [ROPh-PPV], or the like.Polyparaphenylen includes in its category a derivative ofpolyparaphenylen [PPP], poly(2,5-dialkoxy-1,4-phenylene) [RO-PPP],poly(2,5-dihexoxy-1,4-phenylene), or the like. Polythiophene includes inits category a derivative of polythiophene [PT], poly(3-alkylthiophene)[PAT], poly(3-hexylthiophene) [PHT], poly(3-cyclohexylthiophene) [PCHT],poly(3-cyclohexyl-4-methylthiophene) [PCHMT],poly(3,4-dicyclohexylthiophene) [PDCHT],poly[3-(4-octylphenyl)-thiophene] [POPT],poly[3-(4-octylphenyl)-2,2′bithiophene] [PTOPT], or the like.Polyfluorenee includes in its category a derivative of polyfluorenee[PF], poly(9,9-dialkylfluorene) [PDAF], poly(9,9-dioctylfluorene)[PDOF)], or the like.

As another organic compound that can be used for the organic compoundlayers 262 a and 262 b, the following can be used: PFBT, a carbazolederivative, anthracene, coronene, peryrene, PPCP, BPPC, BorylAnthracene, DCM, QD, Eu(TTA)3Phen, or the like.

One kind or plural kinds of the above organic compounds can be used asan organic compound that can be used for the organic compound layers 262a and 262 b.

Next, as shown in FIG. 11B, an insulating layer 264 is formed over thesecond conductive layer 263. Then, a substrate 266 is attached to thesurface of the insulating layer 264.

The insulating layer 264 is preferably formed by coating a compositionusing a coating method and then drying and heating. The insulating layer264 which is provided as a protection layer used at a later peeling stepis preferably an insulating layer with less unevenness on the surface.Such an insulating layer 264 can be formed by a coating method.Alternatively, an insulating film may be formed by a thin-film formingmethod such as CVD or sputtering, and a surface thereof may be polishedby a CMP method to form the insulating layer 264. The insulating layer264 formed using the coating method is formed of the following: anorganic compound such as an acrylic resin, a polyimide resin, a melamineresin, a polyester resin, a polycarbonate resin, a phenol resin, anepoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), afuran resin, or a diallylphthalate resin; an inorganic siloxane polymerincluding a Si—O—Si bond among compounds including silicon, oxygen, andhydrogen formed by using a siloxane polymer-based material typified bysilica glass as a starting material; or an organic siloxane polymer inwhich hydrogen bonded to silicon is substituted by an organic group suchas methyl or phenyl, typified by an alkylsiloxane polymer, analkylsilsesquioxane polymer, a silsesquioxane hydride polymer, or analkylsilsesquioxane hydride polymer. The insulating layer formed by theabove thin-film forming method, which is then subjected to surfacepolishing by a CMP method, is formed of silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, or the like. Theinsulating layer 264 is not necessarily formed, and the substrate 266may be directly attached to the second conductive layer 263.

A flexible substrate which is thin and lightweight is preferably used asthe substrate 266. Typically, a substrate made from PET (polyethyleneterephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone),polypropylene, polypropylene sulfide, polycarbonate, polyetherimide,polyphenylene sulfide, polyphenylene oxide, polysulfone,polyphthalamide, or the like can be used. Moreover, paper made from afibrous material; a multilayer film of a base material film (polyester,polyamide, an inorganic evaporated film, paper, or the like) and anadhesive organic resin film (an acrylic-based organic resin, anepoxy-based organic resin, or the like); or the like can also be used.In the case of using the above substrate, the insulating layer 264 andthe substrate 266 may be attached to each other by providing an adhesionlayer, though not shown, between the insulating layer 264 and thesubstrate 266.

Alternatively, a film having an adhesion layer (made from polypropylene,polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like) whichis attached to an object to be processed by thermocompression may beused as the substrate 266. Such a film can be attached to an object tobe processed by melting the adhesion layer provided in the outermostsurface of the film or a layer (which is not the adhesion layer)provided in the outermost layer of the film by heat treatment and thenby applying pressure thereto. In this case, the adhesion layer is notnecessarily provided between the insulating layer 264 and the substrate266.

Here, the insulating layer 264 is formed in the following manner: acompositing containing an epoxy resin is coated by a coating method, andthen is dried and baked. Next, the substrate 266 is attached over theinsulating layer 264 by thermocompressing the film to the surface of theinsulating layer 264.

Then, as shown in FIG. 12A, the peeling layer 268 and the insulatinglayer 251 are peeled off from each other. In this manner, anelement-formed layer including a memory element and a circuit portion ispeeled from the substrate 250, and transposed to the insulating layer264 and the substrate 266.

Although this embodiment uses a method for peeling the element-formedlayer, in which the peeling layer and the insulating layer are formedbetween the substrate and the element-formed layer, the metal oxide filmis provided between the peeling layer and the insulating layer, and themetal oxide film is weakened by crystallization, the present inventionis not limited thereto. Any of the following methods can also beappropriately used: (1) a method in which an amorphous silicon filmcontaining hydrogen is provided between a substrate having high heatresistance and an element-formed layer, and the amorphous silicon filmis irradiated with laser light or etched to remove the amorphous siliconfilm, thereby peeling the element-formed layer; (2) a method in which apeeling layer and an insulating layer are formed between a substrate andan element-formed layer, a metal oxide film is provided between thepeeling layer and the insulating layer, the metal oxide film is weakenedby crystallization, part of the peeling layer is etched away using asolution or a halogen fluoride gas such as NF₃, BrF₃, or ClF₃, andpeeling is performed at the weakened metal oxide film; (3) a method inwhich a substrate over which an element-formed layer is formed ismechanically removed or is etched away using a solution or a halogenfluoride gas such as NF₃, BrF₃, or ClF₃; or the like. Alternatively, amethod in which a film containing nitrogen, oxygen, or hydrogen (forexample, an amorphous silicon film containing hydrogen, an alloy filmcontaining hydrogen, or an alloy film containing oxygen) is used as apeeling layer, and the peeling layer is irradiated with laser light torelease the nitrogen, oxygen, or hydrogen contained in the peelinglayer, thereby promoting peeling between an element-formed layer and asubstrate, may be used.

By combining the above peeling methods, the transposing step can be moreeasily performed. In other words, peeling can also be performed withphysical force (by a human hand, a machine, or the like) afterperforming laser light irradiation; etching to the peeling layer with agas, a solution, or the like; or mechanical removal with a sharp knife,scalpel, or the like, so as to create a condition where the peelinglayer and the element-formed layer can be easily peeled off from eachother. Moreover, the above peeling methods are examples, and the presentinvention is not limited thereto. By applying the present invention, anelement can be transposed with a favorable state because the element isnot damaged by force applied at a peeling step.

Next, as shown in FIG. 12B, a substrate 275 is attached to the surfaceof the insulating layer 251. The same as the substrate 266 can beappropriately used as the substrate 275. Here, the substrate 275 isattached to the insulating layer 251 by thermocompression of a film.

Note that, after the element-formed Layer including the memory elementis transposed to the substrate 266, the element-formed layer may bepeeled from the substrate 266 again. For example, the element-formedlayer may be peeled from the substrate 250 which is a first substrate,transposed to the substrate 266 which is a second substrate, andtransposed to the substrate 275 which is a third substrate, and then thesubstrate 266 which is the second substrate may be peeled from theelement-formed layer.

As for the memory element 265 a including the first conductive layer 256a, the organic compound layer 262 a, and the second conductive layer 263described in this embodiment, and the memory element 2656 including thefirst conductive layer 256 b, the organic compound layer 262 b, and thesecond conductive layer 263, since adhesion inside each memory elementis favorable, a defect such as film peeling does not occur at aninterface between the layers by force applied at a step of transpositionto the substrate 266 which is the second substrate after the formationover the substrate 250 which is the first substrate. Consequently, thememory element can be peeled off and transposed with a preferable shape,to manufacture a semiconductor device.

As described through the above manufacturing method, the write-oncememory of the present invention using an organic element can bemanufactured over a flexible substrate. Accordingly, it is possible torealize a write-once memory of the present invention where there are fewdefects and no concern for rewriting data, which is superior in anapplication mode.

Note that this embodiment can be implemented by being arbitrarilycombined with Embodiment Mode and Embodiments 1 to 3 described above.

Embodiment 6

Regarding an example of the semiconductor device of the presentinvention, this embodiment will explain an example of a semiconductordevice having a wireless communication function where an organicwrite-once memory is formed over a flexible substrate with reference todrawings. FIG. 13A shows a top view of a semiconductor device of thisembodiment mode, and FIG. 13B shows a cross-sectional view taken along aline X-Y in FIG. 13A.

As shown in FIG. 13A, a memory element portion 404 which is asemiconductor device including a memory element, a circuit portion 421,and an antenna 431 are formed over a substrate 400. A state shown inFIGS. 13A and 13B is in the middle of a manufacturing process, in whichthe memory element portion, the circuit portion, and the antenna havebeen formed over the substrate 400 capable of resisting themanufacturing condition. The material and manufacturing process may beselected in the same manner as Embodiment Mode 4 for manufacturing.

Over the substrate 400, a transistor 441 is provided in the memoryelement portion 404 while a transistor 442 is provided in the circuitportion 421, with a peeling layer 452 and an insulating layer 453interposed therebetween. Insulating layers 461, 454, and 455 are formedover the transistors 441 and 442, and a memory element 443 structured bythe stack of a first conductive layer 457 d, an organic compound layer458, and a second conductive layer 459 is formed over the insulatinglayer 455. The organic compound layer 458 is separated individually byan insulating layer 460 b serving as a partition. The first conductivelayer 457 d is connected to a wiring layer of the transistor 441, sothat the memory element 443 is electrically connected to the transistor441.

In the semiconductor device shown in FIG. 13B, the second conductivelayer 459 is stacked over a wiring layer 456 a and a conductive layer457 c so as to electrically connect to each other. Over the insulatinglayer 455, each of a conductive layer 457 a and an antenna 431 a, aconductive layer 457 b and an antenna 431 b, a conductive layer 457 eand an antenna 431 c, and a conductive layer 457 f and an antenna 431 dare stacked. The conductive layer 457 e is formed in contact with awiring layer 456 b in an opening which is formed in the insulating layer455 so as to reach the wiring layer 456 b, which electrically connectthe antenna to the memory element portion 404 and the circuit portion421. The conductive layers 457 a, 457 b, 457 e, and 457 f under theantennas 431 a, 431 b, 431 c, and 431 d also improve adhesion betweenthe insulating layer 455 and the antennas 431 a, 431 b, 431 c, and 431d. In this embodiment, a polyimide film is used as the insulating layer455, a titanium film is used as each of the conductive layers 457 a, 457b, 457 e, and 457 f, and an aluminum film is used as each of theantennas 431 a, 431 b, 431 c, and 431 d.

Openings (also called contact holes) are formed in the insulating layer455 such that the first conductive layer 457 d and the transistor 441,the conductive layer 457 c and the wiring layer 456 a, and theconductive layer 457 e and the wiring layer 456 b are connected to eachother. Since resistance is decreased as the contact area betweenconductive layers are increased by enlarging the opening, the openingsare set in this embodiment such that the opening for connecting thefirst conductive layer 457 d to the transistor 441 is the smallest, theopening for connecting the conductive layer 457 c to the wiring layer456 a is followed, and the opening for connecting the conductive layer457 e to the wiring layer 456 b is the largest. In this embodiment, theopening for connecting the first conductive layer 457 d to thetransistor 441 is 5 μm×5 μm, the opening for connecting the conductivelayer 457 c to the wiring layer 456 a is 50 μm×50 μm, and the openingfor connecting the conductive layer 457 e to the wiring layer 456 b is500 μm×500 μm.

In this embodiment, distance a from the insulating layer 460 a to theantenna 431 b is greater than or equal to 500 μm, distance b from theend portion of the second conductive layer 459 to the end portion of theinsulating layer 460 a is greater than or equal to 250 μm, distance cfrom the end portion of the second conductive layer 459 to the endportion of the insulating layer 460 c is greater than or equal to 500μm, and distance d from the end portion of the insulating layer 460 c tothe antenna 431 c is greater than or equal to 250 μm. The insulatinglayer 460 c is formed partially in the circuit portion 421; thus, partof the transistor 442 is covered with the insulating layer 460 c and theother part thereof is not covered with the insulating layer 460 c.

By using such a semiconductor device, a power supply voltage or a signalis input directly to the memory element portion 404 from an externalinput portion, so that data (corresponding to information) can bewritten to or read from the memory element portion 404.

In addition, in a case where a signal is not directly input to theexternal input portion 403, a power supply and a signal can be generatedinternally through the RF input portion from an electric wave receivedby the antenna portion, so that data can be read from the memory elementportion 404.

Moreover, the antenna may be provided either so as to overlap the memoryelement portion or so as to surround the memory element portion withoutoverlapping the memory element portion. In the case of overlapping thememory element portion, the antenna may overlap the memory elementportion either entirely or partially. A structure where an antennaportion and a memory element portion are overlapped each other improvesreliability because defective operation of a semiconductor device causedby noise or the like superposed on a signal when communication isperformed by the antenna, or fluctuation or the like of electromotiveforce generated by electromagnetic induction can be reduced. Inaddition, the semiconductor device can also be downsized.

As a signal transmission system in the above semiconductor device thatis capable of transmitting and receiving data in a non-contact manner,an electromagnetic coupling system, an electromagnetic induction system,a microwave system, or the like can be used. The transmission system canbe appropriately selected considering an intended use, and an optimumantenna may be provided in accordance with the transmission system.

For example, when an electromagnetic coupling system or anelectromagnetic induction system (for example, a 13.56 MHz band) is usedas the signal transmission system in the semiconductor device,electromagnetic induction caused by change in magnetic field density isutilized; therefore, a conductive layer serving as an antenna is formedinto an annular shape (for example, a loop antenna) or a spiral shape(for example, a spiral antenna).

When a microwave system (for example, an UHF band (a 860 to 960 MHzband), a 2.45 GHz band, or the like) is used as the signal transmissionsystem in the semiconductor device, the shape such as the length of theconductive layer serving as an antenna may be appropriately setconsidering the wavelength of an electromagnetic wave used for signaltransmission. For example, the conductive layer serving as an antennacan be formed into a linear shape (for example, a dipole antenna), aflat shape (for example, a patch antenna), a ribbon shape, or the like.The shape of the conductive layer serving as an antenna is not limitedto the form of a line; the conductive layer serving as an antenna mayalso be provided in the form of a curve, a meander, or a combination ofthem, considering the wavelength of the electromagnetic wave.

The conductive layer serving as an antenna is formed of a conductivematerial by a CVD method, a sputtering method, a printing method such asscreen printing or gravure printing, a droplet discharge method, adispensing method, a plating method, or the like. The conductive layeris formed with a single-layer structure or a multi-layer structure of anelement of aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold(Au), platinum (Pt), nickel (Ni), palladium (Pd), tantalum (Ta), andmolybdenum (Mo), or an alloy material or a compound material containingthe element as its main component.

In the case of forming the conductive layer serving as an antenna byusing a screen printing method, for example, the conductive layer can beprovided by selectively printing conductive paste in which conductiveparticles each having a particle size of several nm to several tens ofμm are dissolved or dispersed in an organic resin. As the conductiveparticle, a metal particle of one or more of silver (Ag), gold (Au),copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta),molybdenum (Mo), and titanium (Ti), a fine particle of silver halide, ora dispersive nanoparticles can be used. In addition, as the organicresin included in the conductive paste, one or a plurality of organicresins each serving as a binder, a solvent, a dispersant, or a coatingmember of the metal particle can be used. Typically, an organic resinsuch as an epoxy resin or a silicon resin can be used. When forming theconductive layer, baking may be preferably performed after theconductive paste is applied. For example, in the case of using fineparticles (for example, the particle size is greater than or equal to 1nm and less than or equal to 100 nm) containing silver as its maincomponent, as a material of the conductive paste, the conductive layercan be obtained by curing by baking at temperatures of 150 to 300° C.Alternatively, fine particles containing solder or lead-free solder asits main component may be used. In this case, it is preferable to use afine particle having a particle size of less than or equal to 20 μm.Solder or lead-free solder has an advantage of low cost. Moreover,besides the above materials, ferrite or the like may be applied to theantenna.

In addition, in the case of applying an electromagnetic coupling systemor an electromagnetic induction system, and providing a semiconductordevice having an antenna, in contact with metal, a magnetic materialhaving magnetic permeability is preferably provided between thesemiconductor device and the metal. In the case of providing asemiconductor device having an antenna, in contact with metal, an eddycurrent flows in the metal in accordance with change in magnetic field,and a demagnetizing field generated by the eddy current impairs thechange in magnetic field to reduce the communication distance.Therefore, by providing a material having magnetic permeability betweenthe semiconductor device and the metal, eddy current of the metal can besuppressed, thereby suppressing reduction in communication distance.Note that ferrite or a metal thin film having high magnetic permeabilityand little loss of high frequency wave can be used as the magneticmaterial.

Moreover, when providing an antenna, a semiconductor element such as atransistor and a conductive layer serving as an antenna may be directlyformed on one substrate, or alternatively, a semiconductor element and aconductive layer serving as an antenna may be provided over differentsubstrates and then attached to be electrically connected to each other.

As for the memory element 443 including the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459described in this embodiment, since adhesion within the memory elementis favorable, a defect such as film peeling does not occur at aninterface between the layers by force applied at a step of transpositionto the second substrate after the formation over the substrate 400 whichis the first substrate. Consequently, the memory element can be peeledoff and transposed with a preferable shape, to manufacture asemiconductor device.

As described through the above manufacturing method, a semiconductordevice where the write once memory of the present invention isincorporated over a flexible substrate can be manufactured. Such asemiconductor device of the present invention can be used, for example,as an RFID tag. By using the semiconductor device of the presentinvention, data can be added; therefore, historical information or thelike of an object can be made clear by non-contact so as to be of usefor manufacturing, management, or the like. Moreover, since there arefew defects and data is not rewritten, a high level of security isrealized. Further, by forming the write-once memory of the presentinvention over a flexible substrate, an application mode thereof as anRFID tag is expanded remarkably.

Note that this embodiment can be implemented by being arbitrarilycombined with Embodiment Mode and Embodiments 1 to 4 described above.

Embodiment 7

The application of the semiconductor device where the nonvolatile memoryof the present invention is incorporated is widespread, capable of beingapplied to any product as long as it is a product that makes historicalinformation or the like of an object clear by non-contact so as to be ofuse for manufacturing, management, or the like. As shown in FIGS. 14A to14H, a semiconductor device 20 of the present invention can be used bybeing provided for paper money, coins, securities, certificates, bearerbonds, packaging containers, books, recording media, personalbelongings, vehicles, foods, clothing, health products, commodities,chemicals, electronic devices, or the like.

Paper money and coins are money circulated in the market and include inits category ones (cash vouchers) similar to currency that are valid ina certain area, memorial coins, or the like. Securities refer to checks,certificates, promissory notes, or the like (see FIG. 14A). Certificatesrefer to driver's licenses, certificates of residence, or the like (seeFIG. 14B). Bearer bonds refer to stamps, rice coupons, various giftcertificates, or the like (see FIG. 14C). Packaging containers refer towrapping paper for food containers or the like, plastic bottles, or thelike (see FIG. 14D). Books refer to hardbacks, paperbacks, or the like(see FIG. 14E). Recording media refer to DVD software, video tapes, orthe like (see FIG. 14F). Vehicles refer to wheeled vehicles such asbicycles, ships, or the like (see FIG. 14G). Personal belongings referto bags, glasses, or the like (see FIG. 14H). Food refers to foodarticles, beverages, or the like. Clothing refers to clothes, footwear,or the like. Health products refer to medical instruments, healthinstruments, or the like. Commodities refer to furniture, lightingequipment, or the like. Chemical refers to medical products, pesticides,or the like. Electronic devices refer to liquid crystal display devices,EL display devices, television devices (a television receiver or aflat-screen television), cellular phones, or the like.

Forgery can be prevented by the semiconductor device described in theabove embodiment being provided for paper money, coins, securities,certificates, bearer bonds, or the like. In addition, efficiency of aninspection system, a system used in a rental shop, or the like can beimproved by providing the semiconductor device described in the aboveembodiment for packaging containers, books, recording media, personalbelongings, foods, commodities, chemicals, electronic devices, or thelike. Forgery or theft can be prevented by the semiconductor devicedescribed in the above embodiment being provided for vehicles, healthproducts, chemicals, or the like; further, for chemicals, takingmedicine mistakenly can be prevented. The semiconductor device can beprovided by being attached to the surface or by being embedded therein.For example, for books, the semiconductor device may be embedded in apiece of paper; for packages made from organic resin, the semiconductordevice may be embedded in the organic resin. In addition, whensubsequently performing additional writing (postscript) in addition toan optical operation, a memory element provided on a chip is preferablyformed of a transparent material so that a portion thereof can beirradiated with light. Further, forgery can be effectively prevented byusing a memory element which is incapable of rewriting data oncewritten. Furthermore, the problem of user privacy after purchase of aproduct can be solved by providing a system for erasing data of a memoryelement which is provided in the semiconductor device.

In such a manner, efficiency of an inspection system, a system used in arental shop, or the like can be improved by the semiconductor devicedescribed in the above embodiment being provided for packagingcontainers, recording media, personal belongings, foods, clothing,commodities, electronic devices, or the like. In addition, forgery ortheft can be prevented by the semiconductor device described in theabove embodiment being provided for vehicles. Moreover, an individualcreature can be easily identified by the semiconductor device beingimplanted in a creature such as an animal. For example, by thesemiconductor device with a sensor being implanted in a creature such aslivestock, its health condition such as current body temperature as wellas its birth year, sex, breed, or the like can be easily managed.Further, through control to make the communication range of thesemiconductor device short, information being looked at secretly by athird party can be prevented.

As described through the above, the semiconductor device of the presentinvention can be used by being provided for any product. Note that thisembodiment can be implemented by being arbitrarily combined withEmbodiment Mode and Embodiments 1 to 6 described above.

The present application is based on Japanese Patent Application serialNo. 2005-377260 filed on Dec. 28, 2005 in Japanese Patent Office, theentire contents of which are hereby incorporated by reference.

What is claimed is:
 1. A memory device comprising: a memory cell arraycomprising: a plurality of first memory cells; and at least one secondmemory cell; and a circuit for writing data to the plurality of firstmemory cells and the second memory cell, wherein, when the writing ofthe data to one of the plurality of first memory cells fails, thecircuit is arranged to assign an address of the one of the plurality offirst memory cells to the second memory cell and write the data to thesecond memory cell.
 2. The memory device according to claim 1, furthercomprising an antenna which is capable of receiving an electric wave. 3.The memory device according to claim 1, wherein the plurality of firstmemory cells and the second memory cell are arranged to irreversiblychange an electrical resistance thereof when the data is stored therein.4. The memory device according to claim 1, further comprising a secondcircuit for confirming whether the data is normally stored in theplurality of first memory cells.
 5. The memory device according to claim4, further comprising a third circuit coupled with and arranged tocontrol the circuit and the second circuit.
 6. The memory deviceaccording to claim 5, wherein the third circuit is a timing controlcircuit.
 7. The memory device according to claim 1, wherein the memorydevice is formed over a flexible substrate.
 8. The memory deviceaccording to claim 1, wherein each of the plurality of first memorycells and the second memory cell has a thin film transistor comprisingan oxide semiconductor.
 9. The memory device according to claim 8,wherein the oxide semiconductor comprises zinc oxide.
 10. The memorydevice according to claim 8, wherein the oxide semiconductor compriseszinc oxide and is doped with indium.
 11. The memory device according toclaim 8, wherein the oxide semiconductor comprises zinc oxide and isdoped with gallium.
 12. A method for driving a memory device, the methodcomprising: writing data to a plurality of first memory cells;confirming whether the data is normally stored in the plurality of firstmemory cells; and writing the data, which is attempted to be stored inone of the plurality of first memory cells, to a second memory cell ifthe data is not normally stored in the one of the plurality of firstmemory cells.
 13. The method according to claim 12, further comprising astep of receiving electric wave by an antenna portion and generating apower supply to drive the memory device.
 14. The method according toclaim 12, wherein the storage of the data is performed by using anirreversible change of an electrical resistance of the plurality offirst memory cells and the second memory cell.
 15. The method accordingto claim 12, wherein each of the plurality of first memory cells and thesecond memory cell has a thin film transistor comprising an oxidesemiconductor.
 16. The method according to claim 15, wherein the oxidesemiconductor comprises zinc oxide.
 17. The method according to claim15, wherein the oxide semiconductor comprises zinc oxide and is dopedwith indium.
 18. The method according to claim 15, wherein the oxidesemiconductor comprises zinc oxide and is doped with gallium.